Timequest contraints: pseudo-asynchronous case

Are both of your clock enables dividing the clock by the same factor and is the delay constant?

If yes this is what you can do:

Let's say that you have register regA that uses CLK_EN_IN and register regB which uses CLK_EN_OUT.

And let's say that CLK_EN_IN *always* comes 10 clocks before CLK_EN_OUT.

Thus, the combinatory logic you have between A and B has 10 clocks to get the job done and you can use the following constrain to tell TimeQuest about that:

set_multicycle_path -setup -end -from [get_pins reg1|clk] -to [get_pins reg2|*] 10

If this doesn't work out for you then you need to change your design a bit. Adding a layer of registers should suffice.

regA -> complex combinatory logic -> regB -> regC

regA and regB both use CLK_EN_IN, maximizing the allowed delay between regA and regB.

regC uses CLK_EN_OUT; since there's only routing delay between regB and regC, it will achieve fast timings.