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Altera_Forum
Honored Contributor
14 years agoThanks for your answer,
I am using the multicycle command to contraint clock enables in the design, but in this particular case if I use a multicycle I must use a really high multiplication factor (the clock enable is maybe 2000 times slower than the main clock), so that will definitively pass timing. I thing that what I need is to contraint the timing BETWEEN the two clock enables, so I need some sort of outphasing.