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Altera_Forum
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14 years ago

Timequest contraints: pseudo-asynchronous case

Hi all, I am doubtful about how to constraint a few things in a design I have in a Cyclone II FPGA. Basically, the situation is as follows: There is a module A with two processes, Process_...
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Altera_Forum
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14 years ago

If I understood you correctly, you are using only 1 clock and two clock enables.

Then, what you need it set_multicycle_path.