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Study "timequest user guide (
http://www.eet.bme.hu/~nagyg/mikroelektronika/timequest_user_guide.pdf)" or other tutorials. The mentioned document is one of the bests.
you should create a virtual clock which is not connected to any port for set_input_delay and set_output_delay. Examples are available in the mentioned user guide.
You could either create generated clocks manually or use the derive_pll_clocks command in your SDC.
Why do you use the feedback path in PLL?
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Thank you for your reply.
I've read all the documentation available at Altera web site. All the examples of source synchronous output interfaces send data outside of FPGA with clock that drives internal logic.
In my case I use PLL with external feedback to clock RAM chip. There are many reasons of doing this:
1) I don't need to provide clock and data trace delays in my output/input constraints, because the phase skew is compensated by ext. feedback (ext. feedback trace length and Addr/Data trace length are the same)
2) If my board exposed to extreme cold or heat, so trace length are changed - external feedback always compensate these changes of my board traces.
There are more. Like generic design etc.
My problem is - what clock do I pick for set_output_delay constraint. It cant be virtual one, but I also cant pick an internal clock, as it doesn't compensate last FF to pad path. (This internal clock never goes out)
I cant pick a clock that goes out from PLL with external feedback (because I have to tell somehow to TimeQuest about clock relationships....)
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