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Honored Contributor
Honored ContributorTimequest constraints for SRAM
Hello, I've got a board with Stratix V and Synchronous RAM on it. This is how my design looks like (see attachement) First PLL is a Normal mode PLL that clocks desing logic. The second PLL...
Altera_ForumHonored Contributor
Honored ContributorStudy "timequest user guide (http://www.eet.bme.hu/~nagyg/mikroelektronika/timequest_user_guide.pdf)" or other tutorials. The mentioned document is one of the bests.
you should create a virtual clock which is not connected to any port for set_input_delay and set_output_delay. Examples are available in the mentioned user guide. You could either create generated clocks manually or use the derive_pll_clocks command in your SDC. Why do you use the feedback path in PLL?
