Honored Contributor
Honored ContributorHi Josy,
--- Quote Start --- Quartus will add an LE for each instance of a 'kept' signal (after optimization). This extra LE in the input is not optimal especially if the margins are a bit tight. --- Quote End --- Ah, that is a good thing to note. The example above is 'contrived', so I think its time to apply this to my real component :) --- Quote Start --- I renamed the top pins: pin_d to pin_A, pin_sel to pin_B and pin_q to pin_Y to avoid matching *sel* and the like directly. I also added a version of mux_2to1 with registered inputs for 'sel' and 'd' without the 'keep' attribute to see what goes on. Initially this also has an LE to feed the register, but this can be avoided by pushing the register into the IO-cell. --- Quote End --- As soon as an input goes directly to a register, you can search based on the reg|d input, so there is no need for a 'keep' attribute. --- Quote Start --- In real life now most of the times external signals will go direct into a register, and only few will feed a combinatorial circuit. --- Quote End --- My first application of this technique will be for constraining an FTDI FT232H USB-to-FIFO device. In asynchronous FIFO mode the inputs pass through synchronizers, so there is a register that I can use to 'find' the top-level pin. However, in synchronous FIFO mode, the timing requirements of the interface are such that the inputs must feed combinatorially into the FSM, so that the output can be registered (located in an IOE register). I'm writing a document and will post it to the AlteraWiki. --- Quote Start --- One more observation: we have only dealt with a single clock for all instantiated modules. Things get a bit complicated when every instance is fed by a different clock source. This doesn't happen that often though, but I have connected multiple octal ADCs to one FPGA in the past. --- Quote End --- I haven't tried it yet, but I don't see any complication. I think the script can be written to look for the clock, then check if there is a constraint. For example, in FT232H synchronous mode, the FT232H generates a 60MHz clock, hence the SDC constraints file should be able to check for such a constraint - the first time it checks a clock it will not find the constraint, so it can add it - the second check will find the constraint, so move on ... I'll see how these ideas work out in practice sometime this week :) Cheers, Dave
