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Hi Josy,
Thanks to your response I realized what I was missing!
If I add a synthesis keep constraint inside the mux_2to1.vhd component to the combinatorial inputs, i.e.,
attribute keep : boolean;
attribute keep of sel : signal is true;
attribute keep of d : signal is true;
Then the SDC netlist preserves these nodes, and get_pins will return matches to the sel, d[0], and d[1] combinatorial input signals, eg.,
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Quartus will add an LE for each instance of a 'kept' signal (after optimization). This extra LE in the input is not optimal especially if the margins are a bit tight.
I renamed the top pins: pin_d to pin_A, pin_sel to pin_B and pin_q to pin_Y to avoid matching *sel* and the like directly.
I also added a version of mux_2to1 with registered inputs for 'sel' and 'd' without the 'keep' attribute to see what goes on. Initially this also has an LE to feed the register, but this can be avoided by pushing the register into the IO-cell.
In real life now most of the times external signals will go direct into a register, and only few will feed a combinatorial circuit.
One more observation: we have only dealt with a single clock for all instantiated modules. Things get a bit complicated when every instance is fed by a different clock source. This doesn't happen that often though, but I have connected multiple octal ADCs to one FPGA in the past.
Regards,
Josy
Honored Contributor
