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In your example, you are able to search for pattern matches, eg., *|FlagB*|data* or *|SlWr|combout. This means your pin netlist has preserved those signal names, which I suspect are registers in your design.
If I print the entire pins collection for the example design (see the code block below), you will see that it does not contain any of the original input combinatorial signals in the design, eg., the sel control of the multiplexer. You can see the combinatorial inputs to the cells (dataa, datab, etc.), but as I show above, the mapping to the component combinatorial signals changes for each instance (making it impossible to hard-code a path for use in the SDC file).
I suspect that the TimeQuest netlist is just not the right place to look to create the mapping from instance ports to top-level signal ports. The RTL netlist is probably more appropriate, since it preserves the original signal names. Its not too much trouble to get Quartus to run a script that would automate the creation of a Tcl file containing the pin mapping (the pre-flow and post-flow scripts work quite well).
I've filed an Altera Service Request with this zip file, when I get a response from them, I'll post an update.
If you have any other suggestions for TimeQuest tests, let me know and I'll try them!
Cheers,
Dave
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Hi Dave,
FlagB feeds both into a register and into a combinatorial feeding SlWr
I used a keep attribute to preserve the names:
attribute keep: boolean;
attribute keep of FlagB : signal is true;
attribute keep of SlWr : signal is true;
I played a bit around with your zip file in Quartus. I added an SDC file which lists all pins in the design and then searches for specific pins fed by external ports and feeding external ports. As you can see it finds all 'external' ports, but some multiple times. I had to stop here, first I need to do some proper (== eventually paid) work but secondly I don't do much Tcl (I kind of hate it, I always get caught my a missing $ or a mix-up of parenthesis, brackets and braces ... I wish we could use Python instead)
I added a fifth instance, u5 : mux_4to1, defining a tree of basic multiplexers to be able to show a few pins not going to / coming from an external port.
You can see that the reported pin-names are those left after fitting. E.g. if you add registers to the inputs of mux_2to1 you can see that some wil get optimized away by the fitter, although they will still be there in the RTL viewer so I looked in the Schematic Viewer 'post fitting' to find the names of interest.
I attach a .qar (as I do everything in Quartus ...).
Regards,
Josy
Honored Contributor
