TimeQuest Constraints Automation

In your example, you are able to search for pattern matches, eg., *|FlagB*|data* or *|SlWr|combout. This means your pin netlist has preserved those signal names, which I suspect are registers in your design.

If I print the entire pins collection for the example design (see the code block below), you will see that it does not contain any of the original input combinatorial signals in the design, eg., the sel control of the multiplexer. You can see the combinatorial inputs to the cells (dataa, datab, etc.), but as I show above, the mapping to the component combinatorial signals changes for each instance (making it impossible to hard-code a path for use in the SDC file).

I suspect that the TimeQuest netlist is just not the right place to look to create the mapping from instance ports to top-level signal ports. The RTL netlist is probably more appropriate, since it preserves the original signal names. Its not too much trouble to get Quartus to run a script that would automate the creation of a Tcl file containing the pin mapping (the pre-flow and post-flow scripts work quite well).

I've filed an Altera Service Request with this zip file, when I get a response from them, I'll post an update.

If you have any other suggestions for TimeQuest tests, let me know and I'll try them!

Cheers,

Dave

tcl> set col 
_col0
tcl> get_collection_size $col
122
tcl> query_collection -report -all $col
u1|mux_reg|clk
pin_clk~inputclkctrl|outclk
u1|mux_reg|clrn
pin_rstN~inputclkctrl|outclk
u1|mux_reg|d
u1|mux_reg~0|combout
pin_clk~inputclkctrl|inclk
pin_clk~input|o
pin_rstN~inputclkctrl|inclk
pin_rstN~input|o
u1|mux_reg~0|dataa
pin_d~input|o
u1|mux_reg~0|datac
pin_sel~input|o
u1|mux_reg~0|datad
pin_d~input|o
pin_clk~input|i
pin_rstN~input|i
pin_d~input|i
pin_sel~input|i
pin_d~input|i
\g1:u2|mux_reg|clk
\g1:u2|mux_reg|clrn
\g1:u2|mux_reg|d
\g1:u2|mux_reg~0|combout
\g1:u2|mux_reg~0|dataa
\g1:u2|mux_reg~0|datab
pin_d~input|o
\g1:u2|mux_reg~0|datac
pin_d~input|o
pin_d~input|i
pin_d~input|i
u3|u1|mux_reg|clk
u3|u1|mux_reg|clrn
u3|u1|mux_reg|d
u3|u1|mux_reg~0|combout
u3|u1|mux_reg~0|dataa
u3|u1|mux_reg~0|datac
pin_d~input|o
u3|u1|mux_reg~0|datad
pin_d~input|o
pin_d~input|i
pin_d~input|i
u3|u2|mux_reg|clk
u3|u2|mux_reg|clrn
u3|u2|mux_reg|d
u3|u2|mux_reg~0|combout
u3|u2|mux_reg~0|dataa
u3|u2|mux_reg~0|datab
pin_d~input|o
u3|u2|mux_reg~0|datad
pin_d~input|o
pin_d~input|i
pin_d~input|i
u4|\g1:0:u1|mux_reg|clk
u4|\g1:0:u1|mux_reg|clrn
u4|\g1:0:u1|mux_reg|d
u4|\g1:0:u1|mux_reg~0|combout
u4|\g1:0:u1|mux_reg~0|dataa
u4|\g1:0:u1|mux_reg~0|datab
pin_d~input|o
u4|\g1:0:u1|mux_reg~0|datac
pin_d~input|o
pin_d~input|i
pin_d~input|i
u4|\g1:1:u1|mux_reg|clk
u4|\g1:1:u1|mux_reg|clrn
u4|\g1:1:u1|mux_reg|d
u4|\g1:1:u1|mux_reg~0|combout
u4|\g1:1:u1|mux_reg~0|dataa
pin_d~input|o
u4|\g1:1:u1|mux_reg~0|datac
u4|\g1:1:u1|mux_reg~0|datad
pin_d~input|o
pin_d~input|i
pin_d~input|i
u4|\g1:2:u1|mux_reg|clk
u4|\g1:2:u1|mux_reg|clrn
u4|\g1:2:u1|mux_reg|d
u4|\g1:2:u1|mux_reg~0|combout
u4|\g1:2:u1|mux_reg~0|dataa
u4|\g1:2:u1|mux_reg~0|datac
pin_d~input|o
u4|\g1:2:u1|mux_reg~0|datad
pin_d~input|o
pin_d~input|i
pin_d~input|i
u4|\g1:3:u1|mux_reg|clk
u4|\g1:3:u1|mux_reg|clrn
u4|\g1:3:u1|mux_reg|d
u4|\g1:3:u1|mux_reg~0|combout
u4|\g1:3:u1|mux_reg~0|dataa
u4|\g1:3:u1|mux_reg~0|datac
pin_d~input|o
u4|\g1:3:u1|mux_reg~0|datad
pin_d~input|o
pin_d~input|i
pin_d~input|i
pin_q~output|o
pin_q~output|i
pin_q~output|o
pin_q~output|i
pin_q~output|o
pin_q~output|i
pin_q~output|o
pin_q~output|i
pin_q~output|o
pin_q~output|i
pin_q~output|o
pin_q~output|i
pin_q~output|o
pin_q~output|i
pin_q~output|o
pin_q~output|i
u1|mux_reg|q
\g1:u2|mux_reg|q
u3|u1|mux_reg|q
u3|u2|mux_reg|q
u4|\g1:0:u1|mux_reg|q
u4|\g1:1:u1|mux_reg|q
u4|\g1:2:u1|mux_reg|q
u4|\g1:3:u1|mux_reg|q