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Hi all,
Altera's site has the page "Simplify Design Reuse with Dynamic SDC Constraints"
http://www.altera.com/support/examples/timequest/exm-tq-reusable-clock-sdc.html which intriguingly implies that SDC constraints files can be automated.
How is this useful you ask?
Consider the case of a Qsys component that has an associated set of top-level pin constraints, eg., external device setup/hold requirements and clock-to-output delays, or an asynchronous interface that needs timing paths cut. An automated SDC file would find every instance of the Qsys component in the design, map the ports on each component instance to top-level pins, and then setup constraints on those pins. The Qsys component _hw.tcl file can automatically add the SDC file to the project, and since that SDC script would automatically parse the design, the user does not have to do anything to setup the SDC constraints.
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Hi Dave,
I've been using this method a couple of times already, as I too got tired of copy/pasting from/to .sdc files. And it works reasonably OK, the major issue is to find the internal pin name. I haven't done this for multiple instantiations, let alone nested instantiations, of the same module, but I guess it may well work with little changes.
I attach an (annotated) example.
The key will be to name the low-level instantiation adequately to avoid applying constraints to another module, e.g. in my example I have " *|*:reg|Q[*]|q " to match, this name may well occur in other modules, so I'll have to improve on that.
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Caveat/Warning: I searched through all of the .SDC files in the Quartus IP folder and none use the technique described by the Altera link above
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The same applies for the somemegafunction_hw.tcl files, they're hidden in some java or whatever binary package.
Regards,
Josy
Honored Contributor
