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Can you elaborate on why have you not been able to use the method described in the Altera example? I think it explains exactly how to do this.
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It explains how to find the higher-level connections to register ports, i.e., the input, output, clock, or reset pins. If you look in scripts/tmq_find_ports.tcl you'll see that I can find the mapping for these pins.
The Altera example does not explain how to find the mapping between a combinatorial input and a top-level pin (and I'm not sure that it is possible). For example, here's some of the tests in the comments from scripts/tmq_find_ports.tcl
# -------------------------------------------------------------------# Adding -through# ---------------# # The clock, reset, and output path can be identified by using# -through and get_pins to match the top-level signal to the pin# on the register in the cell, i.e., mux_reg|clk, |clrn, and |q.# # The inputs are trickier, as there are 3 signals (sel, d, and# d) feeding combinatorial logic prior to the |d port.# # Using get_pins -comp with a wildcard up to mux_reg showed that# the combinatorial inputs are mux_reg~0|dataa, datab, datac,# datad, and combout. Testing on the different instances shows# that sel d and d connect to different pins in different# instances! If the input mapping was static, eg.,# # mux_reg~0|dataa = sel# mux_reg~0|datab = d# mux_reg~0|datac = d# # Then the script could be automated. However, given that this# mapping is changing, a method of mapping the design inputs# to the cell combinatorial inputs is required.# # As an example, here's the input mappings# # tcl> tmq_find_combin dataa# # u1|mux_reg~0|dataa connects to pin_d# \g1:u2|mux_reg~0|dataa connects to pin_sel# u3|u1|mux_reg~0|dataa connects to pin_sel# u3|u2|mux_reg~0|dataa connects to pin_sel# u4|\g1:0:u1|mux_reg~0|dataa connects to pin_sel# u4|\g1:1:u1|mux_reg~0|dataa connects to pin_d# u4|\g1:2:u1|mux_reg~0|dataa connects to pin_sel# u4|\g1:3:u1|mux_reg~0|dataa connects to pin_sel# # tcl> tmq_find_combin datab# # \g1:u2|mux_reg~0|datab connects to pin_d# u3|u2|mux_reg~0|datab connects to pin_d# u4|\g1:0:u1|mux_reg~0|datab connects to pin_d# # tcl> tmq_find_combin datac# # u1|mux_reg~0|datac connects to pin_sel# \g1:u2|mux_reg~0|datac connects to pin_d# u3|u1|mux_reg~0|datac connects to pin_d# u4|\g1:0:u1|mux_reg~0|datac connects to pin_d# u4|\g1:1:u1|mux_reg~0|datac connects to pin_sel# u4|\g1:2:u1|mux_reg~0|datac connects to pin_d# u4|\g1:3:u1|mux_reg~0|datac connects to pin_d# # tcl> tmq_find_combin datad# # u1|mux_reg~0|datad connects to pin_d# u3|u1|mux_reg~0|datad connects to pin_d# u3|u2|mux_reg~0|datad connects to pin_d# u4|\g1:1:u1|mux_reg~0|datad connects to pin_d# u4|\g1:2:u1|mux_reg~0|datad connects to pin_d# u4|\g1:3:u1|mux_reg~0|datad connects to pin_d# # where mux_2to1 has three combinatorial inputs, the logic cells use# three of four combinatorial inputs, and the logic cell usage# changes for each instance, eg., note how the sel input does not# always map to dataa, and the four generated instances in u4 do not# even map identically.#
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I haven't looked at the ZIP as it looks larger that I can analyze
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Sorry about the length, but I prefer to provide code so as to provide a specific example, either of the problem, or my misunderstanding :)
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but I can say that your example is probably wrong.
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I'd prefer to call it "incomplete" :)
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You may need to add input and output registers to your mux
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That is not possible. The 'real' component that I want to use this with interfaces with an external component, and adding input pipeline registers is not possible.
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Hope this helps
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I appreciate you taking the time to respond, thanks!
Cheers,
Dave
Honored Contributor
