TimeQuest Constraint examples

Ah damn, I just noticed something: with a max delay of 7 ns and a clock period of 4 ns, this will not work -- Quartus will never be able to meet the timing constraints.

All that writing gone to waste...

You need to simply treat DCO as an unrelated base clock, use it to latch the data from the ADC and the use a chain of synchronization registers to pass the data into the adcclk domain.

For constraints, simply use set_false_path or set_clock_groups to cut the paths between DCO and the rest of the clock domains.

create_clock -name dco -period 4 [get_ports dco]

set_false_path -from dco -to adcclk