TimeQuest Constraint examples

Since you're feeding DCO back to the FPGA and using it to latch_data, you need to have it as a non-virtual clock.

Since all those clocks are related, I think it's best to analyze them as such.

Here's how I'd go about it -- for 1 ADC.

A bit of Verilog to illustrate

module an_example (sysclk, sclk, dco, d, q);

input wire sysclk;

output wire sclk;

input wire dco;

input wire d;

output wire q;

wire adcclk;

pll0(.inclk0(sysclk), .c0(adcclk));

assign sclk = adcclk;

reg d_r;

always @ (posedge dco)

d_r <= d;

reg q_r;

always @ (posedge adcclk)

q_r <= d_r;

assign q = q_r;

endmodule

And the .sdc

# Base clock

create_clock -name sysclk -period 20 [get_ports sysclk]

# PLL clocks

derive_pll_clocks

set adcclk {comb_3|altpll_component|auto_generated|pll1|clk[0]}

# # Example for 1 AD7626

# SCLK to ADC

create_generated_clock -source $adcclk -name sclk [get_ports sclk]

# Tricky part: DCO from the ADC # It is derived from the SCLK but has a 0-7 ns delay # (or a bit more if you account for wire delay)# First, create a derived clock with 0 ns delay

create_generated_clock -source sclk -name dco [get_ports dco]# Then use clock uncertainty to represent the 0-7 possible delay

set_clock_uncertainty -from dco -to $adcclk -setup 7.0

# Now we can add I/O delays, referenced to the proper clocks

set_output_delay -clock sclk -min ??? [get_ports cnv]

set_output_delay -clock sclk -max ??? [get_ports cnv]

set_input_delay -clock dco -min 0.0 [get_ports d]

set_input_delay -clock dco -max 1.0 [get_ports d]

# This will calculate the skews and uncertainties for the clocks within the FPGA # the -add is important, otherwise TQ will ignore the uncertainty assignment above and will treat dco as an exact replica of sclk

derive_clock_uncertainty -add