TimeQuest Constraint examples

Thanks for the link to Rysc's document, it will probably be helpful.

I have an external system clock (sysclk) of 50 MHz that is put into a PLL to create a 250 MHz adcclk.

This clock is gated to only generate clock pulses when data is available using ALTDDIO_OUT Module (SCLK). This clock is sent out of the FPGA to AD7626.

Since I use echoed clock mode, the AD7626 responds with an equal clock DCO that is delayed min 0, typ 4 and Max 7 ns.

DCO is used to collect the Data signal from the AD7626.

SCLK or adcclk is used to generate CNV that tells when the AD conversion should start, I guess that CNV should be a little ahead of SCLK to guarantee that SCLK isn't collecting data until the data is ready (after 100 ns).

Currently I have adcclk as a generated clk from the PLL. SCLK is also generated with source from the pll and output after the ALTDDIO_OUT component. DCO is set as a virtual clock in relation to the data pin.

But should there be a relation between SCLK and DCO?

Is the generated clock from ALTDDIO_OUT valid?

SCLK gets a setup time of 2 ns on falling edge from the ALTDDIO_OUT component, which is not what I intended. Should I use multicycle path here?

All clocks are somehow related, but with different delays. I also have 2 AD7626 is the system, both with it's own DCO. Should I group the clocks somehow?