Timequest constrains for async SRAM

You mean truly asynchronous, where you just supply an address and data comes out the other side? (I've seen asynchronous referred to for different scenarios, i.e. if a read_enable signal is the gating signal that gets the data out, then you just treat that as a clock and you can do it, since you really only care about the Tco of this one enable signal). The problem with the truly asynchronous is that your timing is dependent on all the address ports' Tcos.

I looked into this and don't believe it's possible in the "correct" manner, as there's no way to say all the address outputs are physically connected to the data inputs plus some delay. (There was a really ugly method mentioned whereby every address was turned into a clock, and that would work, but it just isn't very elegant.) In the end, you want the fastest Tco and fastest Tsu to determine your clock period. So just keep tightening the constraint on those until you get the best possible results and that's that. Yes, you have to hand calculate your min period, which is basically your Tco + board delays in both directions + memory access times, but this hopefully isn't too big a deal.