Forum Discussion
NuvKFC
Contributor
ContributorTimeQuest can't analysis the clock from the PLL
The problem is as follows.
I need a MUX to switch the clock between normal mode and test mode. And I don't care about any transient state when clock switching.
The ending shows the design. 'pll_...
Hi SyafieqS_Intel, finally, I use the command, /*synthesis keep */, to keep relative port so that TimeQuest can find the CLK[4] port of the PLL.
The CLK[4] port of the PLL in post-fit is "pll|altpll_component|auto_generated|pll1|clk[4]". Thank you, SyafieqS_Intel, very much.
SyafieqS
Super Contributor
Super ContributorHi Kfc,
May I know if there is any updates?
NuvKFCHi SyafieqS_Intel, finally, I use the command, /*synthesis keep */, to keep relative port so that TimeQuest can find the CLK[4] port of the PLL.
The CLK[4] port of the PLL in post-fit is "pll|altpll_component|auto_generated|pll1|clk[4]". Thank you, SyafieqS_Intel, very much.
