Timequest and external intefaces

I like doing -detail full_path when doing report_timing on I/O paths, just because the clock path is so important(in internal paths the clock tree pretty much cancels out between source and destination paths). Not a big deal though.

Anyway, your clock launches at time 0ns and latches at time 7.812ns, which is pretty much your clock constraint and looks correct. In essence, if the external delay were 0ns, you would be asking for a 7..812ns Tco. But, your external delay is 8.5ns. So you need to get your data across in 7.812ns, but the external delay is 8.5ns, so it's pretty much an impossible constraint. You can see this -8.5 subtracted directly as oExt. Now, I don't know what you want it to be, but that's impossible to meet.

Secondly, the -clock in your set_output_delay is the PLL clock. This is incorrect. TimeQuest knows what clock drives the output register. You need to specify the clock externally. I recommend doing a virtual clock like so:

create_clock -period 7.812 -name flash_clk_ext

Then do:

set_output_delay -clock flash_clk_ext 1.0 [get_ports flash_data*]

I made up the 1.0, but if your default requirement is 7.812ns, then subtract the external delay from that for whatever you need the FPGA to do.

(If you need something slower than 7.812, i.e. multicycles, then do something like:

set_multicycle_path -setup -to [get_ports flash_data*] 2

set_multicycle_path -hold -to [get_ports flash_data*] 1

That would make your default setup requirement 2*7.812 and your hold requirement would be 0ns.)

Then in your analysis script do:

report_timing -setup -npaths 30 -detail full_path -to [get_ports flash_data*] -panel_name "s: To flash_data*"

report_timing -hold -npaths 30 -detail full_path -to [get_ports flash_data*] -panel_name "h: To flash_data*"