Timequest and external intefaces

Thanks again for your reply. I used the command that you recommended and the report showed that there was no problem with those paths. I think I have been misunderstanding the summary setup and hold report errors.

I've attached my sdc file and a text file with a report from a failed path in the setup summary, generated using:

report_timing -to_clock {this_organon_sopc|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]} -setup -npaths 10 -detail full_path -panel_name {Setup: this_organon_sopc|the_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]} -file "setup_summary_clk0"

It would be great if someone could explain the steps to take having got this setup summary error. Should I be looking to reduce the fpga clock frequency or have I specified a constraint incorrectly? I hope that once I understand timequest enough to remove one of these errors I will be able to remove them all!