Timequest and external intefaces

Is it Double-Data Rate or Single Data Rate? In general you want to "phase-shift" the clock so that it transitions in the middle of the data eye. Note that only one side needs to do this. For example, if you receive the clock phase-shifted, then you don't have to do it. Or on the flip-side, if the device you're sending data to wants them edge-aligned, then it means they're doing the phase-shift. So you want to phase-shift if the other device isn't doing it.

The reason for doing this is that, besides the shift, you try to match your clock and data delays as closesly as possible. That way they vary together over PVT. If you shift doesn't occur, then regular delays need to be added to get the clock centered on the data, which will vary. For example, with a 10ns data eye, you would need to add 5ns of delay to the clock. To center it, you would probably add something like 7ns in the slow corner, which might be 3ns in the fast corner(making the numebrs up). But as you can see, delays vary over PVT, which cuts into your margins. A PLL phase-shift does not vary over PVT, so if you add 5ns, it will be that way in both timing models.

Now, if your design is single-data rate, then you don't need a PLL, just invert the clock going off chip, or invert the clock driving the data register. Assuming 50/50 duty cycle, this is the same thing as a 180 degree phase-shift. (For DDR interfaces, you want a 90 degree phase shift to center the clock, and this can only be done with a PLL).

Once you do the phase-shift, re-time your design. In fact, set you -max and -min values to 0 as a placeholder, and retime them. What you should see is that your setup requirement is half the data window and your hold requirement is the other half(it will be negative). Then as you increase your -max value from 0, and decrease your -min value, it will cut into this default requirement. Play with it a little to see how it affects setup and hold.