Timequest - Constrating Centre-Aligned SDR

Yes. To be honest, I don't think you need the DDIO on the datapath. It's one of those things I've seen done now and then to more carefully match clock and data, but the SDR output register is really just one of the DDR registers, and the path out is almost identical. I have done a thorough enough analysis, but have never seen a case where going to DDIO registers on data output for an SDR interface is the difference between making timing and not. (In theory, it could even make timing worse). If it is better, it's probably less than 100ps difference.