Timequest - Constrating Centre-Aligned SDR

Okay, quick look at the receive side. First, I'm confused by what you're doing. If you have a PLL in ssync mode, just use "derive_pll_clocks" and don't bother doing the generated clocks. (I dislike that whole vcoph clock in the 28nm PLLs and glad we got rid of it in Arria 10. It just confuses things that don't need to be confusing).

The big thing is you want to say the clock is coming in center-aligned. That can be done by either shifting the external clock 180 degrees or shifting the internal clock 180 degrees. I prefer doing it on the external one, so do:

create_clock -name {sync_data} -period 12.50 -waveform {6.25 12.5}

Then:

create_clock -name {adc_refclk} -period 12.500 -waveform {0.000 6.250} { adc_refclk_in }

Then:

set_input_delay -clock sync_data -max# [get_ports {sync_in}]

set_input_delay -clock sync_data -min# [get_ports {sync_in}]

Let's take the output case where we set them to +/-4.4ns. That means the transmitter skews it by +/-1.85ns. If the board had 0 skew, then we just plug that directly into the set_input_delay:

set_input_delay -clock sync_data -max 1.85 [get_ports {sync_in}]

set_input_delay -clock sync_data -min -1.85 [get_ports {sync_in}]

Now, I'm not accounting for board skew. I'll let you figure that out, but let's say it adds +/-0.6ns. Just increase the set_input_delays by that:

set_input_delay -clock sync_data -max 2.45 [get_ports {sync_in}]

set_input_delay -clock sync_data -min -2.45 [get_ports {sync_in}]

Be sure to run:

report_timing -setup -detail full_path -npaths 50 -to_clock adc_refclk_out -panel_name "setup: ssync out"

report_timing -hold -detail full_path -npaths 50 -to_clock adc_refclk_out -panel_name "hold: ssync out"

report_timing -setup -detail full_path -npaths 50 -from_clock sync_data -panel_name "setup: ssync in"

report_timing -hold -detail full_path -npaths 50 -from_clock sync_data -panel_name "hold: ssync in"

I like to look at the Data Path tab and see how it traces all the delays through the FPGA and uses the clock edges and external delays.