Timequest - Constraining input data paths for minimum skew

Have you tried setting input delay with reference to each of PLL outputs separately?

If you know as well your board delay differences you can accommodate that in your delay settings.

Overall I don't see the feasibility of your approach,FPGA timing tools are not good enough at 1ns resolutions...

another unofficial method is this:

if any output is '1', reset all asynchronously. So only first to rise will have a short pulse provided you latch the decision.