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Altera_Forum
Honored Contributor
Honored Contributortime contain for a driver
hi, I have a divider as following. I usually ignore the timing report for the divider. I started to check those timing report for the divider. There is a hold timing violation as shown in the s...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- That is fine, agree to disagree. My understanding is that the tool is mature enough so that it leave the space for the users to rectify some cases that it cannot solve under its normal rules. Otherwise, what's the point to have the falsepatth option in the constrain? --- Quote End --- commands like false path, multicycle, set input delays ...etc are determined by user. The tool cannot know the internl sampling behaviour of your design or board issues. In future, I assume, it might automatically detect internal multicycle paths or even some false paths by examining your logic and given inputs.
