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Altera_Forum
Honored Contributor
Honored Contributortime contain for a driver
hi, I have a divider as following. I usually ignore the timing report for the divider. I started to check those timing report for the divider. There is a hold timing violation as shown in the s...
Altera_ForumHonored Contributor
Honored ContributorI spent some time on checking the data path. I then realized that this kind of feedback(loopback) is actually launch on one clock and latch on the next clock. Basically, the change of the output is launched on the current clock, but the feedback is latch on the next clock. This is a typical multicycle case. So if I set the the path to be multicycle, and set both setup and hold to be 1. It eliminates the violation.
I think the default setting of the filter is to not to prevent register re-timing, which means register re-timing it is enabled.
