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Altera_Forum's avatar
Altera_Forum
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8 years ago

time contain for a driver

hi, I have a divider as following. I usually ignore the timing report for the divider. I started to check those timing report for the divider. There is a hold timing violation as shown in the s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Have you created the false_path constraints for the reset and any other asynchronous signals? If you don't do this, the tool may report timing violations at these paths. It looks like the path is a data path and the slack is small -0.054. You could try and get the tool fix this by enabling the "Register re-timing" option in Quartus. This will instruct the tool to try and position the registers in your design to try and get rid of the -ve slack and can also get rid of your violations.