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Altera_Forum
Honored Contributor
8 years agoThe result is right in emulator mode, but is wrong in FPGA
My code result is right in emulator mode, but when I compiled it and run in FPGA, the result is wrong. What reasons will cause the problem? And how to debug code in the situation? The code need...
Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- But my code have no global variable that multiple kernels write to it. Is the problem of channel? In my code, many channel read/write have conditions. Or the problem of local memory access?? My local buffer is doubble-buffer, in a loop, there is read and write to it, but their address is different. --- Quote End --- Channel ordering could be the problem, try to print it out. My case was the emulator had the wrong ordering but FPGA was correct.