The result is right in emulator mode, but is wrong in FPGA

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I have not explored this design pattern yet; but is this due to a lack of cache coherence (in the LSUs that are automatically inferred)? Did you ever bring this up with Altera or get a response?

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This is not a bug, this is part of the OpenCL specification. Global memory consistency is only guaranteed at the end of kernel execution and hence, one should not expect consistency when kernels running in parallel are reading from/writing to the same global address. Channels are meant to be used for passing data between kernels, not synchronizing global memory load/stores.