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Altera_Forum
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8 years ago

The result is right in emulator mode, but is wrong in FPGA

My code result is right in emulator mode, but when I compiled it and run in FPGA, the result is wrong. What reasons will cause the problem? And how to debug code in the situation? The code need...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

As I said it could be something in your code, or just a bug in the compiler; it is impossible to know without full analysis of the code and the resulting HDL. You can try opening a support request with Altera and sending them your source code to see what they say.