The result is right in emulator mode, but is wrong in FPGA

--- Quote Start ---

Yes, if you have multiple kernels running in parallel which read from or write to the same global memory buffer, and read/write order will affect your output, you will likely get incorrect results. Trying to synchronize such kernels using channels will NOT work.

--- Quote End ---

But my code have no global variable that multiple kernels write to it. Is the problem of channel? In my code, many channel read/write have conditions. Or the problem of local memory access?? My local buffer is doubble-buffer, in a loop, there is read and write to it, but their address is different.