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Honored Contributor
Honored ContributorThe result is right in emulator mode, but is wrong in FPGA
My code result is right in emulator mode, but when I compiled it and run in FPGA, the result is wrong. What reasons will cause the problem? And how to debug code in the situation? The code need...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- My kernels are all task kernel. That is to say mutiple kernels read/write one global variable ? --- Quote End --- Yes, if you have multiple kernels running in parallel which read from or write to the same global memory buffer, and read/write order will affect your output, you will likely get incorrect results. Trying to synchronize such kernels using channels will NOT work.
