New Contributor
Super ContributorHi Po,
Is it possible for you to share and attach the qar here for me to replicate it (small test case that replicate the error if cannot give the full design) ?
Seem to me like a Quartus issue (likely a bug)
New ContributorHi SyafieqS,
Sorry, I couldn't share the project to you because it contains our confidential ip.
I found that Quartus pro would optimize our clock divider in two different ways, which are shown as follows:
(a) (b)
When I set timing constraints to the output of clock divider in fig. (a), like "get_pins {u_sys0_div2|pos_clk_r_0|q}", Quartus pro would crash.
On the other hand, if I set timing constraints to the output of clock divider in fig. (b), like "get_pins {u_sys0_div2|div_clk_1_u_i_m2_cZ|combout}", Quartus pro would synthesis the design successfully.
I would like to know how I make Quartus pro to optimize my project like fig. (b).
May I have any advice about this issue, please?
