New ContributorI encounter a tricky problem during doing my project. Following is the diagram for the stopwatch_v2, the problem is the counter increases by more than 1 per second (the number output from the counter is 0, 5, 10, 15...), it should increase by 1 per second. I did something wrong? Thanks!
Following are the diagram and VHDL code of LPM_Counter_4Bit:
Regular ContributorHi,
Can you share the design.qar and simulation test bench?
Thanks.
New ContributorHi, please refer to the archived file: Project.qar, and the platform I used is an Altera DE1 Board based on Cyclone® II (specification)
Regular ContributorHi,
What simulation tool you are using? I couldn't find the testbench file in the design. Could you share the steps?
Thanks.
New ContributorHi, the outcome of simulation is correct. I encounter this issue as long as I run it on the board.
Regular ContributorHi,
The simulation ensures the correct functionality of the logic in the design. Upon checking, the design has both setup and hold timing violation. I could not find any sdc file in the project. You have to specify initial timing constraints that describe the clock characteristics, timing exceptions, and signal transition arrival and required times. When your design is free of timing violations, you can be confident that the logic will operate as intended in the target device.
You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf for the SDC constraints
Thanks.
Regular ContributorHi,
May I know if you have any updates?
Thanks.
