The inconsistent results of the Timequest

I'm not completely sure where the hold time on the right comes from. (I could probably figure it out, but if it's a different timing model, then the info on the left wouldn't help. That's another problem with Report Datasheet, in that it doesn't give details so you can check how everything was calculated.) I stick to the hold timing report on the left, since that's what your constraint controls and the fitter is optimizing for.

So stepping back, what does the data coming into the FPGA look like compared to the clock? In essence, you're saying it could hit the FPGA's port up to 500ps before the clock, and so if the data delay to the register isn't at least 500ps larger than the clock delay, we have a hold violation at the register. Is this what's going on in hardware?