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When Rysc says "delays", he means skew, which is how you interpreted it. However, be careful because other delays, e.g. PLL offsets DO affect the setup and hold relationships. A clock crossing between two clocks of the same frequency; one with 0 ps offset and one with 100 ps offset would be treated very differently than a 100 ps clock skew between two identical clocks (due to for example different routing delays on the clocks) with respect to setup and hold relationships.
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Thanks very much. Yes, I think that is Rysc mentioned " are based on how the clocks are described". I think I may express as " are based on how the clocks we configure them". For example, you mentioned PLL offsets DO, that is what we configure the PLL to make an offset in the clock signal, instead of a delay caused by routing.
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