The clock skew does not affect default setup and hold relation, right?

The setup and hold relationships are done independent of delays, and instead are based on how the clocks are described. In essence, you can determine them based on the .sdc, independent of the FPGA it's put into, how it's placed and routed, etc.

Taking your example of 0.001ns delay difference(skew), then you would fix that with a multicycle to push the setup relationship to the next edge. If you then did another place-and-route, and the skew went to -0.001ns, then your multicycle would be wrong, i.e. you would never be able to have the correct constraints due to slight variations in the place-and-route. By having the relationships independent of the place-and-route, you avoid this.