The basic theory about static timing analysis

Excluding very tiny cpld designs and board glue logic, no one is practically supposed to use asynchronous designs in FPGAs and ASICs. The timing tools are meant for synchronous design. The verdict of pass/fail is about speed and is centred on the notion of timing window of clocked registers. The additional delay data given is just informative side issue.

Asynchronous dsign is however a speciality on its own and if successful can be very fast as it is limited only by race condiotions due to variable delays and not by any register timing window. "Achronix" was trying to make special fpgas for very fast asynchronous design that will be programmed as RTL by designer but the tool will convert RTL to asynchronous. I don't know if the idea ever surfaced up.