Testing C17 with JTAG Logic.

Hi guys. Im trying to do some tests in the circuit C17 based on JTAG tecnology. But I'm having some problems with the librarys. I have this code for Xilinx FGPAs:

library IEEE;use IEEE.std_logic_1164.all;
library work;
--use work.package.all;
library selfext;
use work.gates_pkg.all;
use work.fflop_pkg.all;

but this doens't work on quartus II

Error (10481): VHDL Use Clause error at c17.vhdl(6): design library "work" does not contain primary unit "gates_pkg"

Error (10800): VHDL error at c17.vhdl(6): selected name in use clause is not an expanded name

Error (10481): VHDL Use Clause error at c17.vhdl(7): design library "work" does not contain primary unit "fflop_pkg"

Error (10800): VHDL error at c17.vhdl(7): selected name in use clause is not an expanded name

Error: Quartus II Analysis & Elaboration was unsuccessful. 4 errors, 0 warnings

How can I replace this librarys? Thank you for the help.