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Honored Contributor

8 years ago

Testbench for 10G Ethernet PHY

Hello, I just implemented a 10G Ethernet PHY design using the IP core: "1G/2.5G/5G/10G Multi-rate Ethernet PHY" + pll & reset controller. The Ethernet PHY core should receive the serial data fro...

Altera_Forum

Honored Contributor

8 years ago

I suggest you refer to this Stratix 10 Low Latency Ethernet 10G MAC Design Example User Guide

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug-20073.pdf

Chapter 6: 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices

It provides an example to run the simulation.

Regards,

skbeh

(This message was posted on behalf of Intel Corporation)

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Testbench for 10G Ethernet PHY

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