tco requirement inside design

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Hi I'm trying to setup a tco requirement assignment between the clock and a multiplier output(not a pin). i was able to do it while there was a outputPin but now i need it between ff's. classic timing report says ignored due "no path found" or "no such node in netlist" or "synthesised away".

do i need additional assignments?

thanks in advance

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Hi,

why do you want to specify a tco for an internal signal ? When you set your clocks Quartus will take care about your internal tsu, tco ...

Kind regards

GPK

i dont know if tco is the right assignment for this.

i want to set the input-to-ouput delay between 6-9ns.

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i dont know if tco is the right assignment for this.

i want to set the input-to-ouput delay between 6-9ns.

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Hi,

do you have a path between a FPGA input and FPGA output which contains only logic ?

Kind regards

GPK