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Altera_Forum
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13 years ago

TCL Macro for Top-Level Schematic to Verilog Conversion (For ModelSim Simulation)

I put together a little TCL script that automatically converts a schematic top-level entity to Verilog to help streamline preparation for ModelSim. (This script improves the native Quartus b2v...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Thanks for the feedback Rysc. I just tried out your tip and I see how it totally improves the b2v inst# naming, very nice.

I like the pre-flow script idea, putting the "source b2vFixer.tcl" in the .qsf seemed to work, but it seemed a little kludgy having to hand edit this file.

When I have some more time I'll try putting together an alterawiki page for it.