Takes too long to get address

I implemented the code you gave me:

architecture structure of framestore is
	signal hold: std_logic_vector(3 downto 0);
	signal address: std_logic_vector(14 downto 0);
	signal next_address: std_logic_vector(14 downto 0);
	signal cont: std_logic;
	
	component ram4bits is
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (14 DOWNTO 0);
		clock		: IN STD_LOGIC  := '1';
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
	end component;
begin	
	process(clk,reset,valid,readEn)
	begin
		if(reset = '1') then
			next_address <= "000000000000000";
			cont <= '0';
		elsif(clk'event and clk = '1') then
			cont <= valid OR readEN;
			next_address <= address + '1';
		end if;
	end process;
	
	store: ram4bits port map(address,clk,input,valid,hold);
	
	output <= hold when readEn = '1' else "0000"; --self explanatory
	address <= next_address when cont = '1' else rwaddressstart;
	
	addressout <= address;
	
end structure;

and it actually gave me the same result as what I had before (the first piece of data that gets read from memory gets read for two clock cycles).

From a hardware level, I'm not sure I understand what this does differently. What do you mean when you say something is registered? Does that mean it's stored in a register? Does that make things slower? Why is something here not stored in a register and something in my code was? Why do I need cont for example? Why can't I just directly say address <= next_address when readEn ='1' or valid = '1'? Why do I even need the process at all? Why can't I say address <= address + '1' when etc.?

Thanks