Forum Discussion
Altera_Forum
Honored Contributor
16 years agoI previously mentioned, that you have also the option to register none of the RAM block input signals, because they are already registered in the RAM. This would be my preferred method to achieve a fast design reaction.
process(clk,reset)
begin
if(reset = '1') then
next_addr <= (others => '0'); -- not actually required
cont <= '0';
elsif(clk'event and clk = '1') then
cont <= valid OR readEn;
next_addr <= address + '1';
end if;
end process;
store: ram4bits port map(address => address,clock => clk,data => input,wren => valid,q=>hold);
address <= next_addr WHEN cont = '1' ELSE
rwaddressstart;