Forum Discussion
Altera_Forum
Honored Contributor
16 years agoThe valid signal and the input are synchronous. When the valid signal arrives, that's when I want to start writing to memory. I can't just make my input one cycle delayed because my input shows up with the valid signal. I'll go back to one edge sensitivity. I just would like to figure out how I can have valid and input line up as they are, and have it still work.