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My input and valid appear to arrive at exactly the same time
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Yes. Now input is one clock cycle too early.
In my opinion, you have added more confusion with the edge detection working on both clock edges. It doesn't seem correct the way you're doing it.
Personally, I would proceed like this:
- determine if all input signals are clock synchronous, otherwise provide synchronisation registers
- sketch a timing diagram of existing input signals and expected/intended design reactions
- check if it's feasible considering the used IP, in this case the RAM block
- use a synchronous, single clock edge process as design basic
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