SystemVerilog Interface Synthesis Quartus 13

I was pleasantly surprised the continuous assignment worked

for the /AddrThreshold/ expression. But it doesn't work for the

other uses cases, like:

    logic  pipe_a, pipe_b;

Best I can tell, I wont be able to use the parameters that are

part of the interface. I will need to reduplicate all the parameters

to the module:

    module avalon_mux
   # (
       MaxAddress = 16,
       DW = 16
    )
    (
        interface bus
    );
    
        localparam AddrThreshold = MaxAddress/2;
        logic  pipe_a, pipe_b;
    
        always @(posedge bus.clock) begin
            if (busin.address <= AddrThreshold) begin
                pipe_a <= bus.writedata;
            end else begin
                pipe_b <= bus.writedata;
            end 
        end 
    
    endmodule

And then instantiate like:

avalon_mux 
  # (MaxAddress=bus.MaxAddress, DW = bus.DW)
   M1(bus);

which partially defeats the purpose of using interfaces.

Regards,

Chris