SystemVerilog Interface and Design Partitions

It appears that Quartus (including the latest v15.0) does not look at modports when determining the direction of the ports in SystemVerilog interface blocks.

The fitter complaints that the design uses bidrectional ports basically ignoring the modport definition.

This problem appears when the interface block connects the two design partitions. It doesn't appear when the interface block is buried within the design partition. I have not tried turning on the optimization across design partitions, but then I do not want to do that. Since I get design blocks from other team members and also I'd like to lock down the placed and routed netlist within a partition.

Anyone else face similar problem? Any suggestions?

Thank you.

Best regards,

Sanjay