SystemVerilog const definition issue manifested in quartus_map

I am running into an issue with a SystemVerilog constant defined in a package that manifests itself during quartus_map. It is very possible that I have misunderstood the SystemVerilog specification, but I have been able to simulate the design correctly. It is also possible that I have misunderstood what is supported in Quartus v11.0, but from what I can tell, everything requiring support for my particular case (packed arrays, const, packages, compilation unit) is supported.

Here are the messages I get during quartus_map:

Warning (10036): Verilog HDL or VHDL warning at my_example_pkg.sv(38): object "c_my_example_seeds" assigned a value but never read

Critical Warning: Net "work.my_example_pkg.c_my_example_seeds_*__*_" has a missing source. The net will be connected to GND and its default value will be ignored. ==> where * equals every element in my 2-D packed array.

Any ideas?

Here is the SystemVerilog HDL that results in the issue:

my_example_pkg.sv

-------------------------

`ifndef MY_EXAMPLE_PKG

`define MY_EXAMPLE_PKG

package my_example_pkg;

const logic [31:0][63:0] c_my_example_seeds = {

64'h0000_00ff_ffff_ffff,

64'heeee_eeee_0000_ee00,

64'h00dd_0000_dddd_dddd,

64'hcccc_cccc_cc00_0000,

64'h00bb_0000_bbbb_bbbb,

64'haaaa_aaaa_0000_aa00,

64'hf000_0000_0000_0000,

64'h0000_aaaa_aaaa_ffff,

64'h9999_0000_9999_9999,

64'h8888_0000_8888_8888,

64'h7777_7777_7777_0000,

64'h5555_6666_0000_0000,

64'h0000_1234_0000_0000,

64'h0000_0000_fedc_ba98,

64'h0000_0000_7654_3210,

64'h0123_4567_ffff_ffff,

64'heeee_eeee_89ab_cdef,

64'hf0f0_0f0f_dddd_dddd,

64'hcccc_cccc_e1e1_1e1e,

64'hd2d2_2d2d_bbbb_bbbb,

64'haaaa_aaaa_c3c3_3c3c,

64'hb4b4_4b4b_9999_9999,

64'h8888_8888_a5a5_5a5a,

64'h9696_6969_7777_7777,

64'h6666_6666_8787_7878,

64'h600d_c0de_5555_5555,

64'h4444_4444_0bad_0bad,

64'hdead_beef_3333_3333,

64'h2222_2222_0d06_f00d,

64'hface_fac7_1111_1111,

64'hba55_0000_ffff_ffff,

64'hffff_ffff_0000_fade

};

endpackage

import itoe_my_example_pkg::*;

`endif

my_example_design.sv

-----------------------------

`include "utils_pkg.sv

`include "my_example_pkg.sv"

module my_example_design

(

// ports not shown

);

// only posting relevant code where constant c_my_example_seeds is used

genvar ref_i;

generate for (ref_i=0; ref_i<32; ref_i++) begin : g_ref_data_arr

always_ff @(negedge rstb or posedge clk)

begin

if (!rstb) ref_data_arr_reg[ref_i] <= c_my_example_seeds[ref_i];

else if (!cfg_en) ref_data_arr_reg[ref_i] <= c_my_example_seeds[ref_i];

else if ( (ref_i==id) & ready & valid)

ref_data_arr_reg[ref_i] <= lfsr64(ref_data_arr_reg[ref_i]); // lfsr64 defined in utils_pkg.sv

end

end endgenerate

endmodule