SystemVerilog compile guards and macros

TL;DR - If you have the exact problem as me use the following statement in the .qsf:

set_global_assignment -name VERILOG_CU_MODE MFCU

OK, so I've managed to understand what's happening.

In general, the scope in which a macro is defined called "Compilation Unit". Older Quartus verisons and newer Quartus lite/std versions use Multi File Compilation Unit (MFCU), while Quartus Pro (starting from 18 probably) uses Single File Compilation Unit (SFCU) by default.

What's the difference?

MFCU means the compilation unit includes ALL of the files, while SFCU includes only each single file. Macros from a different file CAN be defined with SFCU, but only using `include <file> macro.

SFCU is required for Quartus to auto-sort the compilation order of files. It's rational - in order the determine the compilation order, each file should be viewed separately by Quartus (It's as if Quartus regards them all in parallel), So we can't expect the order in which the files are listed to affect the compilation of a single file and hence the compilation order (it's a logic loop =)). SFCU also make macros safer - only what you explicitly include (either via `include or using global macro assignment) is defined.

Unfortunately in order for the macro guards to work GLOBALY we have to use MFCU mode instead (Again, this is rational as I explained). Adding the following statement in the .qsf does the trick:

set_global_assignment -name VERILOG_CU_MODE MFCU

After compiling with this statement, Quartus will throw a warning about turning off the auto-discovery feature (this is the automatic compile order feature I've mentioned above).

As the build system my team use explicitly order the files by their compilation order I'm fine with this.

Thanks for the help, and thanks for Intel Forums, Google (and my tenacity ) to find the answer.