Forum Discussion
James_B
Contributor
ContributorSystemVerilog Cast Syntax in Quartus 20.1
Platform: Windows 10, Quartus 20.1 Standard
I have a design in which I used the SystemVerilog cast operators, and synthesis failed:
However, when I revert to old style cast operators, ...
It appears that Quartus does not support SystemVerilog modports, and also is not planning on supporting VHDL 2019 interfaces which support view. Thus, any struct(SystemVerilog) or record(VHDL) must have all members as either in or out direction when using them on a portlist, that is my conclusion to all of this.
sstrell
Super Contributor
Super ContributorI've never used this before, but is "signed" technically a data type you can convert to with a cast?
https://www.chipverify.com/systemverilog/systemverilog-datatypes
Has it worked elsewhere for you?
