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RRoma13
New Contributor
New Contributorsystem verilog signed'() extended sign bit wrong
module signed_test3( input logic clk, input logic [11:0] in, input logic [11:0] zero, output logic signed [15:0] d, output logic signed [15:0] d2 ); logic signed [15:0] c,c2; logic signed [...
paveetirrasrie_Altera
Frequent Contributor
Frequent ContributorJust wanted to check with you, is your concern has been addressed?
If yes , kindly do let me know.
Thank You
